1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly to a method of enlarging the tip portion of fin-shaped structure.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the FinFET can be controlled by adjusting the work function of the gate.
As the semiconductor industry enters 10 nm node generation, the importance of critical dimension (CD) of fin-shaped structure within a device has increased significantly. In current fabrication process for FinFET device, the fin-shaped structures disposed on the core region and the fin-shaped structures disposed on the input/output region preferably share same critical dimension. However, it has been noted that it would be more desirable for the devices on core region to have greater critical dimension for increasing the channel volume while it would be more advantageous for devices on input/out region to have smaller critical dimension for improving short channel effect and the current architecture clearly cannot satisfy the demand on both regions at the same time. Hence, how to effectively resolve this issue has become an important task in this field.